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1 p/n:pm0706 1. introduction the purpose of this application note is to describe the implementation of a pci bus master 100 base-tx fast ethernet node using mxic highly integrated single chip fast ethernet nic controller MX98715BEC. in details, this document presents product overview, programming guide, hardware design and layout recommendations that can help you to quickly and smoothly implement a fast ethernet adapter card. as you can find in the MX98715BEC driver diskette, mxic already provideds a complete set of high quality drivers for easier and more efficient way to interface with MX98715BEC on the most popular network operating systems. nevertheless, there are still some special ap- plications or environment not covered in the MX98715BEC driver diskette. driver developers, how- ever, could still refer to the section of driver program- ming guide to accomplish the required driver. it is rec- ommended that you should be familiar with the MX98715BEC data sheet before reading this guide. 2. product overview the MX98715BEC implements the 10/100mbps mac layer and physical layer on a single chip in accordance with the ieee 802.3 standard. 3. hardware design considerations 3.1 system application block diagram a system block diagram for the MX98715BEC based fast ethernet adapter card is shown as following: MX98715BEC application note preliminary rev. 0.2, nov. 30, 2000 MX98715BEC pci bus osc or crystal 25mhz eeprom boot rom led magnetic rj45 fig. 1 the MX98715BEC highly integrates with direct pci bus interface, including pci bus master with dma channel capability, direct eeprom as well as boot rom inter- face, and large on chip transmit/receive fifos. also, the MX98715BEC is equipped with intelligent ieee802.3u-compliant nway auto-negotiation capability allowing a single rj-45 connector to link with the other ieee802.3u-compliant device without re-configuration. to optimize operating bandwidth, network data integrity and throughput, the proprietary adaptive network throughput control (antc) function is implemented. for detailed product specification information, please refer to the MX98715BEC data sheet.
2 p/n:pm0706 rev. 0.2, nov. 30, 2000 MX98715BEC 3.2 pci connection the MX98715BEC provides direct pci bus interface to pci connector. board designers should especially take care of the four pins of tdi,tdo,prsnt1# & prsnt2# that are only related to pci bus connector. boards that do not implement jtag boundary scan should tight tdi and tdo together to prevent the scan chain from being broken. both pins prsnt1# and prsnt2# should be con- nected to ground indicating that the board physically exists in a pci slot and provids information about the total power requirements ( less than 7.5w ) of the board. 3.3 oscillator or crystal the MX98715BEC is designed to operate with a 25mhz oscillator or crystal module. the clock specification of this oscillator should meet 25mhz +/- 50ppm. 3.4 boot rom the MX98715BEC support a direct boot rom interface allowing diskless workstations to remotely download op- erating system from network server. for proper opera- tion, the access time of adapt eprom should not ex- ceed 240ns. 3.5 serial eeprom the MX98715BEC provides pins eecs,bpa0 (eeck), bpa1 (eedi) and bpd0 (eedo) for directly accessing the serial eeprom. bpa0-1 and bpd0 serve as sk (eeck), di (eedi) and do (eedo) respectively. the contents of the eeprom includes the id information of the MX98715BEC (vendorid, deviceid, sub-vendorid, sub-deviceid and mac id), and the configuration pa- rameters for software driver. the eeprom contents should be programmed according to mxic's definition as mentioned in appendix a. detailed software program- ming example is described in section 4.5. 3.6 programmable led support the MX98715BEC provides five pins led[0:4] to con- trol display leds. displayed messages are program- mable through setting csr9 bits[31:28] & bit24. the maxi- mum sinking current of these output pins is 16ma. cur- rent limiting resistor (560 ohm) should be added to en- sure proper operation. the following indicates the con- figuration setting table for led display programming. csr 9 <28> 0 1 led 0 activity link speed csr 9<29> 0 1 led 1 good link link activity csr 9<30> 0 1 led 2 link speed colision csr 9<31> 0 1 led 3 receive f/h duplex csr 9<24> 0 1 led 4 colision pmeb 3.7 network interface to magnetic component for isolating and impedance matching purpose, an iso- lating transformer with 1:1 transmit and 1:1 receive turns ratio is required for transmit and receive twisted pair interface. in appendix b, several transformers that we had verified successfully with MX98715BEC are listed for quick reference purpose. 3.8 optimized equalizer components mxic fast ethernet solution utilizes adaptive equal- izer to compensate the attenuation and phase distor- tion induced by different lengths of cable. to optimize transmit and receive signal quality, pins rtx should be connected to external resistors 1k ohm ( 1%) and then to ground respectively. 3.9 remote-power-on and acpi application MX98715BEC fully supports remote-power-on and acpi spec that meet pc99 requirement for power- sensitive applications. it accepts the following wake-up events in the power-down mode. * reception of a magic packet. * reception of a network wake-up frame. * detection of change in the network link state. to put MX98715BEC into the sleep mode and enable the wake-up events detection are done as following:
3 p/n:pm0706 rev. 0.2, nov. 30, 2000 MX98715BEC 4. driver programming guide this chapter will provide you the necessary information for programming driver for the MX98715BEC based node. initialization module is introduced first that describes how MX98715BEC is initialized before any other operations can commence, then followed by actual implementation examples for both transmit and receive operations. 4.1 initialization initializethetransmitring() { unsigned int i,j; unsigned long physicaladdress; for (i=0; iownership=0x00; tx_resource[i]->tstatus=0x0000; tx_resource[i]->tdes0_unused=0x00; /* fill buffer_1_address tdes2 */ get_ea((void far *)(tx_resource[i]->tx_buffer_data), &physicaladdress); tx_resource[i]->buff_1_addr=physicaladdress; /* fill buffer_2_address tdes3 */ if (i==numtxbuffers-1) j=0; else j=i+1; get_ea((void far *)(tx_resource[j], &physicaladdress); tx_resource[i]->buff_2_addr=physicaladdress; } } initializethereceivering() { unsigned int i,j; unsigned long physicaladdress; for (i=0; iframe_length=rdes0_own_bit; rx_resource[i]->rstatus=0x0000; /* fill rdes1 */ rx_resource[i]->command=rdes1_buff- rx_buffer_size+rxpkt_size[i]; /* fill buffer_1_address rdes2 */ get_ea((void far *)(rx_resource[i]->rx_buffer_data), &physicaladdress); rx_resource[i]->buff_1_addr=physicaladdress; /* fill buffer_2_address rdes3 */ if (i==numrxbuffers-1) j=0; else j=i+1; get_ea((void far *)(rx_resource[j], &physicaladdress); 1. write 1 to ppmcsr [8] to enable power management feature. 2. write the value to ppmcsr [1:0] to determine which power state to enter. if d1, d2 or d3 hot state is set, the pc is still turned on and is commonly called entering the remote wake-up mode. otherwise if the main power on a pc is totally shut off, we call that it is in the d3 cold state or remote power-on mode. to sustain the operation of the lancard, a 5v standby power is required. once the pc is turned on, MX98715BEC loads the magic id from eeprom and sets it up automatically. no register is needed to be programmed. after then, simply turn off pc to enter d3 cold state. in either remote wake-up mode or remote power- on mode, the transceiver and the rx block are still alive to monitor the network activity. if one of the three wake- up events occured, the following status is changed: 1. ppmcsr [15] (pme status) is set to 1. 2. crs5 [28] (wkupi) is set to 1. 3. pci interrupt pin inta# is asserted low. 4. lanwake pin is asserted high.
4 p/n:pm0706 rev. 0.2, nov. 30, 2000 MX98715BEC rx_resource[i]->buff_2_addr=physicaladdress; } } initialize() { unsigned long physicaladdress; nic_read_reg(&csr6); nic_write_reg(&csr6,csr6.value&(~(csr6_sr|csr6_st))); delay(200) : //wait tx&rx to enter stop state, or you can //check bit17~bit19 (rx state) & bit 20~bit21 (tx state) in //csr5 to assure this condition. initializethetransmitring (6); initializethereceivering (6); nic_write_reg(&csr0,csr0_l_swr); delay(50); nic_write_reg(&csr0,csr0shadow); //csr0 shadow=0xfe58a000 get_ea((void far *)rx_resource[0],&physicaladdress); nic_write_reg(&csr3,physicaladdress); get_ea((void far *)tx_resource[0],&physicaladdress); nic_write_reg(&csr4,physicaladdress); nic_write_reg(&csr7,csr7shadow); //csr7shadow=9xe7ffa06d nic_write_reg(&csr16,csr16shadow); //csr16shadow=0x0b2c000 //clear status register nic_write_reg(&csr5,(unsigned long)0xffffffff); nic_write_reg(&csr6,csr6shadow); //csr6shadow=0x01a8e202 setup_frame(tdes1_setup_last,perfect); //initialize cam to accept self-address/broadcost address //fromes } 4.2 transmission module bmtx() { unsigned char editmode, j; struct tx_resource *tx_pointer; initialize(); fill_pattern(6); //fill pattern nic_write_reg(&csr6,csr6.value&(~csr6_st)); //stop nic_read_reg(&csr6); nic_write_reg(&csr6,csr6.value|csr6_sf); //store and forward nic_read_reg(&csr0) nic_write_reg(&csr0,csr0.value|0x020000); //tap=01 tx_pointer=tx_resource[0]; j=0; editmode=1; while (editmode) { if ((tx_pointer->ownership & 0x80)==0) { j++; j%=tx_pkt_num; if (tx_pointer->command & tdes1_ls_bit) tx_error_detect(tx_pointer->tstatus); tx_pointer->ownership |= 0x80; tx_pointer=tx_resource[j]; } if (kbhit()) { keycode_get(); if (m_code!=0) { switch (m_code) { case 0x1b: // esc: quit editmode=0; break; case 0x20: nic_read_reg(&csr6); nic_write_reg(&csr6,csr6.value^csr6_st); break default: break; } } } } } 4.3 reception module bmrx() { unsigned char editmode,i,j; unsigned long physicaladdress; struct rx_resource *rcv_pointer; initialize(); rcv_pointer=rx_resource[0]; j=0; editmode=1; while (editmode) { // if data received
5 p/n:pm0706 rev. 0.2, nov. 30, 2000 MX98715BEC if ((rcv_pointer->frame_length & 0x8000)==0) { j++; j%=6; if (rcv_pointer->rstatus & rdes0_ls) rx_error_detect(rcv_pointer->rstatus); rcv_pointer->frame_length |= 0x8000; rcv_pointer=rx_resource[j]; } if (kbhit()) { keycode_get(); if (m_code!=0) { switch (m_code) { case 0x1b: // esc: quit editmode=0; break; default: break; } } } } } 4.4 special coding of MX98715BEC 4.4.1 speed selection speed selection for MX98715BEC is controlled by inter- nal nway registers. the internal nway registers are removed and protocol selection is controlled by operation mode register (csr6) and 10base-t control register (csr14) nway active 100f 100h 10f 10h csr6_ps 0 1 1 0 0 csr6_pcs x 1 1 x x csr6_fd 1 1 0 1 0 csr14_ane 1 0 0 0 0 4.4.2 registers setting for developing your own driver the contents of csr16 for mxic 10/100base nic con- trollers should be set differently as follow: MX98715BEC = 0x0b2cxxxx meanwhile, you could directly access the nway auto- negotiation status from csr20. detailed format infor- mation please refer to MX98715BEC data sheet. 4.5 eeprom accessing the following is a reference code for accessing the con- tents of eeprom that stores id information and node configuration for the MX98715BEC. /************************************* * read all content from eeprom **************************************/ eeprom_read() { unsigned int i, address, eeval; char bit; for (address=0; address<64; address++){ nic_write_reg(&csr9,(unsigned long)0x04800); eeprom_serial_in(0); eeprom_serial_in(1); //command eeprom_serial_in(1); eeprom_serial_in(0); for(i=0; i<6; i++){ //address serial in bit = ((address>>(5-i)) & 0x01) ? 1:0; eeprom_serial_in(bit); } eeval=0; for(i=0; i<16; i++){ //dat serial out nic_write_reg(&csr9,(unsigned long)0x04803); nic_read_reg(&csr9); eeval += (((unsigned long)0x008 & csr9.value)>>3)<<(15- i); nic_write_reg(&csr9,(unsigned long)0x04801); } nic_write_reg(&csr9,(unsigned long)0x04800); c46[address*2] = eeval & 0x0ff; c46[address*2+1] = (eeval >>8) & 0x0ff; } } /************************************* * write a word to eeprom **************************************/ eeprom_write(unsigned int address, unsigned int data) { unsigned int i; char bit; eeprom_wen(); nic_write_reg(&csr9,(unsigned long)0x04800); eeprom_serial_in(0); eeprom_serial_in(1); //command eeprom_serial_in(0); eeprom_serial_in(1);
6 p/n:pm0706 rev. 0.2, nov. 30, 2000 MX98715BEC for(i=0; i<6; i++){ //address serial in bit = ((address>>(5-i)) & 0x01) ? 1:0; eeprom_serial_in(bit); } for(i=0; i<16; i++){ //data serial in bit = ((data>>(15-i)) & 0x01) ? 1:0; eeprom_serial_in(bit); } nic_write_reg(&csr9,(unsigned long)0x04800); nic_write_reg(&csr9,(unsigned long)0x04801); i=0; do{ i++; nic_read_reg(&csr9); } while ((!(csr9.value & 0x08)) && (i<10000)); nic_write_reg(&csr9,(unsigned long)0x04800); if (i==10000) prstr ing (wr iting eeprom error !!); eeprom_wds(); } eeprom_wen() { nic_write_reg(&csr9,(unsigned long)0x04800); eeprom_serial_in(0); eeprom_serial_in(1); eeprom_serial_in(0); eeprom_serial_in(0); eeprom_serial_in(1); eeprom_serial_in(1); eeprom_serial_in(0); eeprom_serial_in(0); eeprom_serial_in(0); eeprom_serial_in(0); nic_write_reg(&csr9,(unsigned long)0x04800); } eeprom_wds() { nic_write_reg(&csr9,(unsigned long)0x04800); eeprom_serial_in(0); eeprom_serial_in(1); eeprom_serial_in(0); eeprom_serial_in(0); eeprom_serial_in(0); eeprom_serial_in(0); eeprom_serial_in(0); eeprom_serial_in(0); eeprom_serial_in(0); eeprom_serial_in(0); nic_write_reg(&csr9,(unsigned long)0x04800); } /************************************* * serial inject a bit to eeprom **************************************/ eeprom_serial_in(unsigned int bit2) { nic_write_reg(&csr9,(unsigned long)0x04800+4*bit2); nic_write_reg(&csr9,(unsigned long)0x04803+4*bit2); nic_write_reg(&csr9,(unsigned long)0x04801+4*bit2); } 4.6 auto-compensation on transceiver the driver must set bits csr20<9> and csr20<14> high to enable auto-compensation function. be careful not to clear these two bits while accessing crs20 at any time.
7 p/n:pm0706 rev. 0.2, nov. 30, 2000 MX98715BEC 5. pcb layout recommendation introduction: due to the high frequency and the increasing degree of integration, system board designs are becoming complex. the purpose of this section is to give system designer more information. such as power stability, placement, signal trace routing and de-coupling capacitor. 5.1 power / ground consideration it is recommended to separate power plane into 3 domains (power for digital , analog and receive section). seg- mented power supplies reduces noise from one section to another. it is also recommended to separate ground plane into 3 domains ( digital ground, analog ground and receive ground). the reason for separating is to prevent digital noise from coupling onto the analog or receive ground. all power/ground lines should be as wide as possible to allow noise de-coupling and efficient low resistive paths for supply current. depending upon the environment, any or all of these filters may be simplified.o 3.3v v analog v digital v receive bead bridge gnd gndr gnd gnda pci interface gnd (digital ground) gnda (analog ground) gndr (receive ground) 40mil
8 p/n:pm0706 rev. 0.2, nov. 30, 2000 MX98715BEC 5.2 board layout / trace routing 90 degree corners should be avoided, smooth cornering is preferred. keep the lengths of clock lines short and minimize the numbers of vias. all pair lines ( i.e. tx+/- , rx+/-) are of the equal length and run in parallel then possible noise is common and can be ignored on different inputs. a good practice is that never run transmit and receive pair too close. crosstalk may become a problem. the ground shield of clock line may reduce extra noise. tx+ tx- magnetic magnetic tx+ tx- magnetic magnetic tx+ tx- tx+ tx- rx+ rx- rx+ rx- o sc ill a t or ground shield tx+ tx- rx+ rx-
9 p/n:pm0706 rev. 0.2, nov. 30, 2000 MX98715BEC all differential pair ( tx +/ - , rx +/-) to the magnetic should have matched impedance. see schematics for details. a chassis ground is used to isolate the cable side and ground. 5.3 component placement general: external components are placed as close as possible 100 ohm tx+ tx- rx+ rx- magnetic system ground chassis ground magnetic magnetic rj-45 bootrom osc/crystal eeprom ic 50 50 v v
10 p/n:pm0706 rev. 0.2, nov. 30, 2000 MX98715BEC de-coupling capacitor de-coupling cap should be placed close to power pin. it stabilize current to the device and de-coupling noise from the power plane to ground. 0.1 u pin ic analog region receive region digital region 82. vdd 83. gnd 88. gnd others 85. vdd 84. gnd 89. vdd 94. vdd 95. gnd 90. gnd 97. vdd 96. gnd 91. vdd 103. vdd 100. gnd 105. vdd 101. gnd 104. gnd 106. gnd MX98715BEC rx- rx+ tx- tx+ bead bead osc or crystal 25mhz 128 111 receive region analog region 94 106 93 88 85 82 80 digital region 1 fig. 2 transformer
11 p/n:pm0706 rev. 0.2, nov. 30, 2000 MX98715BEC appendix a: eeprom format byte offset (hex) descriptions 00-13 reserved 14 mac id byte0 ( is automatically loaded into ic ) 15 mac id byte1 ( is automatically loaded into ic ) 16 mac id byte2 ( is automatically loaded into ic ) 17 mac id byte3 ( is automatically loaded into ic ) 18 mac id byte4 ( is automatically loaded into ic ) 19 mac id byte5 ( is automatically loaded into ic ) 1a magic packet id byte0 ( is automatically loaded into ic ) 1b magic packet id byte1 ( is automatically loaded into ic ) 1c magic packet id byte2 ( is automatically loaded into ic ) 1d magic packet id byte3 ( is automatically loaded into ic ) 1e-39 reserved 3a magic packet id byte4 ( is automatically loaded into ic ) 3b magic packet id byte5 ( is automatically loaded into ic ) 3c-59 reserved 5a lsb of sub-device id ( is automatically loaded into ic ) 5b msb of sub-device id ( is automatically loaded into ic ) 5c lsb of sub-vendor id ( is automatically loaded into ic ) 5d msb of sub-vendor id ( is automatically loaded into ic ) 5e-65 reserved 66 bit0 : must be 0, modem interface disable 67 bit0 : crunen : control the functionality of clkrunb pin 0 : MX98715BEC always refuses to slow or stop the clock 1 : MX98715BEC will agree to slow or stop the clock bit1 : trdysel : ibm bridge bug fix bit4 : hwdiswol : disable the wake-on-lan feature bit7 : mishw7 : select the power of pmd while system power up. 1 : power on the pmd. 0 : power down the pmd. 68 mldthre1 [5 : 0] bit0~bit5 loaded into csr33 [11 : 6] 6a mldthre3 [5 : 0] bit0~bit5 loaded into csr33 [23 : 18] 6b mldthre2 [5 : 0] bit0~bit5 loaded into csr33 [17 : 12] 6c mldthre2 [5 : 0] bit0~bit5 loaded into csr34 [23 : 18]
12 p/n:pm0706 rev. 0.2, nov. 30, 2000 MX98715BEC led programing option table 01 led0sel act speed led1sel link link/act led2sel speed col led3sel rx full/half led4sel col pmeb 77 miscellaneous options is automatically loaded into csr21 register & ic. : bit0:mphitdis : set 1 to disable magic packet detection loaded into csr21.2 bit1:lnkchgdis : set 1 to disable link packet detection loaded into csr21.3 bit2:retry bug fix. bit3:wkfcaten, wake up frame catenation enable. 78-79 reserved, and should be set to 0 7a lsb of device id 7b msb of device id 7c lsb of vendor id 7d msb of vendor id 7e-7f reserved, and should be set to 0 6d mgcthre1 [5 : 0] bit0~bit5 loaded into csr34 [17 : 12] 6e mvcrthre2 [5 : 0] bit0~bit5 loaded into csr34 [11 : 6] 6f mvcpthre1 [5 : 0] bit0~bit5 loaded into csr34 [5 : 0] 70 network id index: to indicates the starting address of network id in length of continu- ous 6 bytes. the content of this field could be in the range of 00-04h, or 10-14h, or 21- 24h, or 31-34h. ic always automatically load id from 14h after reset or power up. 71-75 reserved, and should be set to 0 76 led option: the conent of this field is automatically loaded into csr9 register for led option. bit0:csr9<28>=led0sel bit1:csr9<29>=led1sel bit2:csr9<30>=ledsel2 bit3:csr9<31>=ledsel3 bit4:csr9<24>=ledsel4 bit5:csr9<25>:wkfcat0 bit6:csr9<26>:wkfcat1 bit7:must be zero
13 p/n:pm0706 rev. 0.2, nov. 30, 2000 MX98715BEC appendix b: special components 1.magnetic a.basic electrical specification turn ratio transmit 1:1 receive 1:1 ocl 350uh min measured between 0 and 70 c with a 0.1v rms, 100khz signal at a dc. bias between 0 and 8ma. ll 0.4uh max at >1mhz cww 18pf max dcr 0.9w max per winding isolation resistance not less than 1gw @ 2000v rms isolation voltage 2000v rms min @ 60hz for 1 min rise/fall time 3ns min 4ns max insertion loss (100 khz to 100 mhz) -1.1 db max cmdr & dcmr (100 khz to 80 mhz) 38 db min cross talk (100khz to 80 mhz) -38 db max b. transformer reference vendors vendor part no valor st6118 (pt4171s) pe pe68515 belfuse s558-5999-15 delta lf8200 taimic hsip-002 2.crystal a. basic electrical specification c l =((c1*c2)/(c1+c2))+c ic + c, rd 100 ohm, r 1m ohm c l =crystal's external load capacitor specified by crystal's specification cic=MX98715BEC internal capacitor, 7pf c=pcb's stray capacitance assume c 1 =c 2 =c ext , c=3pf, c l =1/2c ext + 7pf + 3pf if cl=20pf, than c ext =c 1 =c 2 =20pf. c2 rd r ic c1
14 p/n:pm0706 rev. 0.2, nov. 30, 2000 MX98715BEC 3. special requirement on resistors & bead resistors for rtx=1k ohm 1% ferrite bead maximum current capacity for analog vdd > 300ma ferrite bead maximum current capacity for receive region vdd > 100ma b. crystal reference vendors spk 25mhz 50ppm ndk jen jaan enterprise
15 p/n:pm0706 rev. 0.2, nov. 30, 2000 MX98715BEC revision history revision description page date 0.0 mar/27/2000 0.1 modify pcb recommendation p7 jul/11/2000 0.2 modify analog region receive region & fig.2 p10 no v/30/2000 modify special requirement on resistors & bead p14
m acronix i nternational c o., l td. headquarters: tel:+886-3-578-6688 fax:+886-3-578-2888 europe office: tel:+32-2-456-8020 fax:+32-2-456-8021 japan office: tel:+81-44-246-9100 fax:+81-44-246-9105 singapore office: tel:+65-347-8385 fax:+65-348-8096 taipei office: tel:+886-2-2509-3300 fax:+886-2-2509-2200 m acronix a merica, i nc. tel:+1-408-453-8088 fax:+1-408-453-8488 chicago office: tel:+1-847-963-1900 fax:+1-847-963-1909 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice. 16 MX98715BEC MX98715BEC c9930 ta777001 taiwan top side marking line 1 : mx98715b is mxic parts no. "e" : pqfp "c" : commercial grade line 2 : assembly date code. line 3 : wafer lot no. line 4 : state

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